Expert on the high-speed line wiring FAQ [posted].
Experts on high-speed lines, wiring questions. .
1. How to handle the actual wiring in some theoretical issues of conflict.
Q: In the actual wiring, many theories are conflicting; such as: 1. Handle multiple analog / digital to the wiring: in theory, should be isolated, but in practice small, high-density wiring, because of space limitations or absolute isolation will lead to small-signal simulation to take the line is too long Connection theory difficult to achieve. My approach is: the analog / digital function modules split into a complete island, the function module analog / digital ground are connected in this island. And through the channel to the island and "large" connected. I wonder if this is correct? 2.In theory, crystal oscillator and CPU line should be short, because the structure layout, crystal oscillator and CPU line longer, thinner and, therefore, is that the work is not stable, then how to solve this problem from the wiring? more many, especially considering the high speed PCB wiring in EMC, EMI, there are many conflicts, it is a headache, how do I resolve these conflicts? thanks!.
A: 1. . Basically, the analog / digital split of isolation is right. Note that the signal to go across the line as far as possible not to have separate areas (moat), and not to allow power and signal return current path (returning current path) become too large. 2. .Crystal is a simulation of the positive feedback oscillation circuit, to have a stable oscillation signal, must meet the loop gain and phase of specifications, while the analog signal of the oscillation of the specification are susceptible to interference, even with the ground guard traces may not completely isolate the interference. And too far, plane noise can also affect positive feedback oscillation circuit. So, be sure to set the oscillator and distance into the chip may be *. 3. Really high speed cabling and EMI requirements there are a lot of conflict. But the basic principle is that the added resistance due to EMI capacitor or ferrite bead, can cause some electrical characteristics of the signal does not meet specifications. Therefore, the best to use the arrangement and the PCB stack alignment techniques to solve or reduce EMI issues, such as high-speed signal to go inner. Last resistor and capacitor or ferrite bead with a way to reduce the damage to the signal. .
2. At the high-speed design, how to solve signal integrity problems? wiring is how to implement? only one output clock signal line, how to implement wiring?.
A: The signal integrity is basically impedance matching problem. Factors affecting the signal source impedance matching structure and the output impedance (output impedance), take the line characteristic impedance, load characteristics, the alignment topology (topology) structure and so on. Solution to this is the * termination (termination) and adjust the alignment of the topology. Differential pair routing has two points to note, first, the length of two lines the same length as far as possible, and the other is the distance between the two lines (the distance from the differential impedance of the decision) to have remained unchanged, that is, to maintain the parallel.Parallel mode there are two, one two go in the same alignment layer (side-by-side), one of the two lines and the two layers (over-under). General former side-by-side realization way more. Wiring must be the signal source and the receiver also are differential signals can be meaningful. So only one output clock signal is the inability to use the wiring.
3. On high-speed differential signal routing. .
Q: on the PCB * nearly parallel go high speed differential signal pairs, impedance matching, as the two lines of mutual coupling, will bring many benefits. But the view was expressed that this will increase the signal attenuation, affecting the transmission distance. Is this is not the case, why? I in some big company's evaluation board, seen as a high-speed cabling * near and parallel to, but intentional so that the two-line distance to come, I don't understand that an effect is better. My signal 1GHz above, impedance of 50 ohms. Calculated in software, the differential pair is 50 ohms to calculate it? Or 100 ohms to count? Differential line receiver on a match between the possibility of additional resistance? Thank you! . .
A: makes high-frequency signal attenuation was conducting its own resistance characteristics (conductor loss), including skin effect (skin effect), another is a dielectric material of dielectric loss. These two factors in the analysis of transmission line effects of electromagnetic theory (transmission line effect), we can see them on the signal attenuation. Coupled differential lines will affect their own characteristic impedance, becomes smaller, according to partial pressure principles (voltage divider) This will send the signal source line voltage smaller. As for signal attenuation due to coupling Ershi theoretical analysis I have not read, so I can not comment. Differential pair wiring should be properly * near and parallel. * Near the so-called appropriate because it will affect the spacing differential impedance (differential impedance) value, this value is the difference on the important design parameters.Also because the parallel need to maintain the consistency of the differential impedance. If two lines come, differential impedance will be inconsistent, it will affect the signal integrity (signal integrity) and latency (delay timing). Differential impedance computation is 2 (Z11-Z12), Z11 is the alignment of its own characteristic impedance, Z12 are two differential line because coupling impedance, arising from and related to line spacing. So, you want to design a 100 ohm differential impedance, the alignment of its own characteristic impedance must be slightly larger than 50 ohm . The larger the amount of available simulation software figure out. .
4. Q: q: to enhance immunity, in addition to the analog and digital power point only in separate connections, bold ground and power lines, expects to some good comments!.
A: In addition to to separate the isolation, we have to pay attention to some of the power analog circuits, if the sharing of power with digital circuits, it is best to add filtering circuit. In addition, the digital signal and analog signals do not have staggered, in particular, not across the division to place (moat). .
5. High-speed PCB design signal layer blank area deposited copper grounding problems.
Q: In the high-speed PCB design, signal layers can be deposited copper blank area, then the number of signal layers are deposited copper is the ground is good, or half of the ground, half of the power supply is good? . .
A: in a blank area of the vast majority of deposited copper is grounded. Only in high-speed signal line side deposited copper when deposited copper and signal line distance, since the application of copper will reduce the alignment of the characteristic impedance. Have to be careful not to affect the characteristic impedance of its layers, such as dual stripline structure.
6. The matching of high-speed signal lines. .
Q: in high-speed plate (e.g. p4 motherboard) layour, why ask high-speed signal line (such as CPU data address signal line) to match the? if it does not match what's hidden? its match length range (both signal line delay variance) what factors determine what?.
A: The requirement traces characteristic impedance matching of the main reasons is to avoid the effects of high-speed transmission line (transmission line effect) caused by the reflection (reflection) affect the signal integrity (signal integrity) and the delay time (flight time). That is if you do not match, then the signal will be reflected affect its quality. All traces of the length of the range are based on timing (timing) requirements set out. Affect the signal delay time of factors, only one length away.P4 require certain signal cable length in a range based on the signal transmission mode (common clock or source synchronous) calculated timing margin, assigning part to alignment length tolerance. As for the above two patterns of temporal calculation, limited to the time and length is not convenient to go into the details, please go to the following network http://developer. .intel. com/design/Pentium4/guides download "Intel Pentium 4 Processor in the 423-pin Package / Intel 850 Chipset Platform Design Guide". Which "Methodology for Determining Topology and Routing Guideline" section discussed in the context. .
7. Q: in high-density printed circuit board through the software automatically generates test points normally meets the mass production of the test require? add test points will not affect the quality of high-speed signal?.
A: Most software automatically generates test points are to meet the test requirements have to look on the plus points of the normative test whether the test equipment requirements. Also, if the alignment is too close and add more stringent test point specifications, there may be no way to automatically add each piece of wire test points are, of course, need to manually append the place to be tested. But will the increase affect the signal quality depends on the way and signal test points in the end be fast. Basically, plus the test points (not perforated both online (via or DIP pin) when the test point) may be added on-line or short line from the line pull out.The former are coupled with a very small capacitance on-line, the latter is more of a branch. These two conditions will towards high-speed signal will have some impact on the frequency of the signal with the speed and rate of change of signal edge (edge rate). Effect size can be learned through simulation. In principle, the testing point as small as possible (and of course also meet the requirements of the test equipment) branches as short as possible.
8. How to Select PCB board? How to avoid high-speed data transfer to the surrounding small-signal modeling of high frequency interference, is there some design of the basic ideas? Thank you. .
A: select the PCB Board must meet the design requirements and available capacity and the cost of intermediate chanxing balance. Design requirements include electrical and bodies of the two parts. Usually in the design of very high-speed PCB Board (greater than GHz frequency), this material will be more important. For example, now commonly used FR-4 material, in several GHz frequencies of dielectric loss dielectric loss of signal attenuation is greatly affected, you may not use it. It is necessary to pay attention to the electrical, dielectric constants (dielectric constant) and dielectric loss in the design of the suitability of frequency . Avoid high-frequency interference basic idea is to minimize the interference of high frequency electromagnetic fields, also known as crosstalk (Crosstalk). Available high-speed signals and widening the distance between the analog signal, or add ground guard / shunt traces in the analog signal next. Also note that digital to analog ground noise. .
9. Well known PCB including many layers, layers of meaning I wasn't very clear. Mechanical, keepoutlayer, topoverlay, bottomoverlay, toppaste, bottompaste, topsolder, bottomsolder, drillguide, drilldrawing, multilayer these layers do not know their exact meaning. I hope you teach.
A: In the EDA software terminology, there are many not have the same definition. Following the literal meaning may be explained. .
Mechnical: General multifingered plate machined dimensioning layer.
Keepoutlayer: define not go line, play piercing (via), or put parts of the region. These limitations can be handled separately defined. Topoverlay: unable to know its meaning from the literal. Provide some more information to further discussion. .
Bottomoverlay: unable to know its meaning literally. You can provide some information to further discussion.
Toppaste: top need some solder paste on the exposed copper. .
Bottompaste: tongpi underlying need to expose some of the paste.
Topsolder: shall mean the top solder mask layer to avoid the maintenance of the manufacturing process or in the future may not careful, short Bottomsolder: shall mean the bottom solder layer. .
Drillguide: pore size may be different, the corresponding symbol, the number of a table.
Drilldrawing: finger holes bitmap, will have a different aperture corresponding symbol. .
Multilayer: there should be no separate this layer, can refer to a multilayer PCB, the single-panel and one pair of panels is concerned.
10. A system is often divided into a number of PCB, a power supply, interface board, every board interconnection between the ground often have led to the formation of many of the loop, resulting in such low-frequency loop noise, I do not know how to solve this problem ? . .
A: each PCB Board connected between the signal or power in action, for example, when A Board has power or signal send to B Board, will have the same amount of current from A laminar flow back to the Board (this is Kirchoff current law). This formation will find impedance smallest local flow back. Therefore, in all regardless of power or signal connected interfaces, assigned to strata pins cannot be too little, to lower the impedance, which can reduce the formation of noise. Alternatively, you can analyze the entire current loop, especially the larger part of the current, adjust the access stratum or ground methods to control the current moves (for example, in the manufacture of low-impedance somewhere, so most of the current from this places to go), to reduce other, more sensitive signal. .
11. (1) whether or not to provide some empirical data, formulas, and methods to estimate the wiring impedance. (2) when does not meet the requirements of impedance matching, is at the end of the signal wire with parallel matching resistance is good, or at the signal cable plus matching resistor in series. (3) the differential signal line whether plus ground wire in the middle.
A: 1. . Here are two commonly refer to the characteristic impedance of the formula: a. . Microstrip line (microstrip) Z = (87 / [sqrt (Er +1. .41)]) Ln [5. .98 H / (0. .8 W + T)] where, W is width, T is the thickness of traces of copper, H line to the reference plane to go the distance, Er is the dielectric constant of PCB board materials (dielectric constant ). This formula must be 0. .1 <(W / H) <2. .0 And 1 <(Er) <15 the situation can be applied. b. .Ribbon cable (stripline) Z = [60/sqrt (Er)] ln {4H/[0.67 π (T + 0. .8W)]} where h is the distance between the two reference plane and alignment is located in the middle of the two reference plane. This formula must be in the W/H <0。.35及t><0。.25的情况才能应用。 > It is calculated by simulation software is more accurate.
2. . Select termination (termination) of the method has a number of factors to consider: a. . Signal source (source driver) of the structure and strength. b. . Power consumption (power consumption) in size. c. . On the time delay effect, this is the most important point to consider. So hard to say which way is better termination. .
3. differential signaling intermediates are generally cannot be combined with the ground. Because of the differential signal applications the most important thing is to take advantage of the difference signal between coupling (coupling), such as flux cancellation, noise (noise immunity) capacity, etc. If in the middle with the ground, would destroy the coupling effect.
12. To introduce some foreign high-speed PCB design on the level of the current processing capacity, processing level, processing materials and related technical books and information? . .
A: the application of high-speed digital circuits are communications network and computers, and other related areas. With respect to the communications network, the operating frequency of PCB Board has already reached GHz and down again I know there are as many as 40 layers. Computer related applications but also because the chip's progress, whether it is general PC or server (Server), the Board of the maximum operating frequency also has reached 400MHz (Rambus) above. In response to this demand for high-speed high-density alignment, blind buried vias (blind / buried vias), mircrovias and the build-up process technology demand has gradually increased. These design requirements are manufacturers can mass production. Here are several good technical books: 1. . Howard W. . Johnson, "High-Speed Digital Design - A Handbook of Black Magic"; 2. . Stephen H. .Hall，“High-Speed Digital System Design”； 。.
3. . Brian Yang, "Digital Signal Integrity";. .
13. The flexible circuit board design and processing.
The company intends to adopt flexible circuit board designed to address small-scale imaging system signal transmission and circuit boards each other to pass on. I ask whether the design of rigid-flexible board design software for specific needs and specifications? Where can undertake such other domestic circuit board processing? Thank you. .
Answer: you can use the General design of the PCB software to design flexible circuit board (Flexible Printed Circuit). Gerber format as used for production of FPC manufacturers. Due to the manufacturing process and General PCB manufacturers, their manufacturing capacity for minimum line width, minimum line distance, the smallest aperture (via) has its limitations. In addition, you can turn the flexible circuit board shop more be reinforced. As for production companies can "FPC" when the keyword query should be able to find.
14. . PCB routing adjustments. .
I would like to ask a question: because sleep machine cloth unhappiness, but adjusting up. I usually use manual wiring, while they are engaged in most of the PCB to pin density large SMD chips and take bus (CBUS ABUS, DBUS, etc.), as a result of the work of the higher frequency, which leads to the shortest possible. nature is very dense signal cable uniform in a small area on the Board. I now feel the time more adjusting these density of signal lines, adjust the distance between lines, uniform as possible. Because the routing process, both now and in General to change lines. Each time we re-uniform change has been announced for each root a good line spacing. The more cloth to the end, this more and more. Second, adjust line width, so that a certain width of only put in as much as possible to increase in the new line. Usually a line, there are a lot of bending, a bend is a hand only a period of adjustment to adjust them too time-consuming. I think if in the process of wiring can be thought by my first cursory hand-pull, is over, the software helped me in these two areas can be adjusted automatically. Or even have finished fabric, such as to change lines, change is cursory look, then let the software adjust.Or even, in the end I need to resize the component package, meaning the whole cabling needs adjustment, allowing software to do it. It will be much faster. I am using Protel98. I know this software can do automatic adjustment components packaged symmetrical distance do not automatically adjust the line spacing and line width. Perhaps some of the functionality I will not use, or any other way, in this advice.
answer: from the line width and density affect the alignment of two important factors. Usually high frequency board design, the wiring need to decide before the alignment of the characteristic impedance. PCB stacked in the fixed case, the characteristic impedance will determine the line of the line width. The pitch is, and crosstalk (Crosstalk) size of any relation. Minimum acceptable spacing determined by the time the signal crosstalk delay and signal integrity effects are acceptable. This is the smallest line simulation software can be done from the pre-simulation (pre-simulation) are.In other words, the wiring is required before the line width and minimum line distance should have been decided on, and cannot be retained, since it will affect the characteristic impedance and crosstalk. That is what most of the EDA wiring do autorouting in the software or the adjustment does not go to the line width and minimum line distance. If the minimum line width and line spacing is set in routing software, wiring or adjustment of easy reading software engine capacity and weak. If you are interested in short Expedition company see our winding engine, please call 21-64159380, will serve you.
15. . On the high-speed digital PCB. .
Ask the appropriate choice of PCB and shell grounding point of principle? also, General PCB LAYOUT engineers always according to the DESIGN GUIDE/LAYOUT GUIDELINE, I want to know more about the General Development GUIDE is hardware/system engineer, senior engineer or PCB? who should be on board-level system performance primarily responsible. Thank you!..
answer: with the case then the principle of site selection is the use of chassis ground provides a low impedance path to the return current (returning current) and the control of the return current path. For example, the usually high-frequency clock generator devices or nearby can be fixed with a screw through the strata and the PCB to connect chassis ground to do in order to minimize the current loop area, thus reducing electromagnetic radiation. Who should be responsible for the development guideline may have different circumstances of each company have different arrangements.Guideline development must be for the whole system, chip, circuit action principle sufficient understanding to develop in line with the electrical specification and the realizable guideline. Therefore, in my personal opinion, hardware, system engineers seem to be more suitable for this role. Of course, the senior PCB engineer can provide practical implementation experience, makes this guideline can achieve better.
16. Circuit board that several aspects should be DEBUG. .
Q: the Board design, production, and DEBUG should several aspects from the start.
Answer: digital circuits, the first order of first determine three things:. .
1. confirm that the size of the value of all the power supply shall meet the design requirements. Some multi-power system might require some power between the order and speed up some code.
2. . Make sure all the clock signal frequency signals are working properly and there is no risk of non-monotonic (non-monotonic) problem. .
3. to confirm the reset signal meets the regulatory requirements.
These are normal, then the chip should be issued the first cycle (cycle) of the signal. Next, the operation principle and in accordance with the system bus protocol to debug. .
17. now commonly used electronic PCB design software to meet the requirements of anti-interference?.
Q: What are the PCB design software, how to PROTEL99 reasonable requirements designed to meet their own PCB. . Such as how to meet the requirements of high-frequency circuits, how to consider the interference meet the requirements of the circuit? Thank you!!. .
A: I am not using Protel experience, the following is only for discussion of design principles.
High-frequency digital circuits mainly on account of transmission line effects on signal quality and timing (timing) effects. Such as the characteristic impedance of the continuous and matching, the choice of termination method, topology (topology) mode choice, the length of the alignment and spacing, the clock (or strobe) signal skew the control. .
If the device has been fixed, the General immunity is to widen the spacing or ground guard traces.
18. About lvds signal wiring. .
Q: for lvds low voltage differential signaling is, in principle, of equal length and parallel wiring, but more difficult to achieve, can provide some experience? your product has a trial version?.
A differential signal wiring requirements and so long and when the parallel reasons the following:. .
1. a parallel objective is to ensure the integrity of the differential impedance. Parallel to the spacing of the different places that differential impedance discontinuities.
2. . So long you want to ensure that the purpose of timing (timing) accuracy and symmetry. Because the differential signal timing with the two signal intersections (or relative voltage difference), and if unequal length, then the intersections do not appear in the signal amplitude (swing amplitude) in the middle, can also cause the adjacent two time intervals (time interval) asymmetry, increasing the difficulty of timing control. .
3. length will increase the common mode signal (common mode), impact of signal integrity (signal integrity).
19:. .
Q: in the circuit board size fixed, if the design of the need to accommodate more functionality, they often need to increase the density PCB alignment, but this may lead to the alignment of mutual interference, go too impedance cannot reduce, experts in high speed (> 100MHz) and high-density PCB design tips.
A: In high-speed high-density PCB design, the crosstalk (crosstalk interference) is indeed a special attention because of its timing (timing) and signal integrity (signal integrity) has a great influence. Here are a few pay attention to:. .
1. control the alignment of the characteristic impedance of continuous and matching.
2. . Go line spacing size. General often see double spacing width. Can go through the simulation to know the line spacing on the timing and signal integrity effects, to identify the minimum tolerable distance. The result of different signals may be different chips. .
3. Select the appropriate termination method.
4. . To avoid the alignment of two adjacent up and down the same direction, even just walking up and down lines overlap together, because the crosstalk level than the adjacent alignment with the case still great. .
5. use of buried and blind hole (blind/buried via) to increase the alignment of the area. However, PCB production costs will increase.
In the actual implementation is indeed difficult to achieve fully parallel and equal length, but still have to try to make it. In addition, you can reserve differential termination and common mode termination to ease on the timing and signal integrity. .
20. power filtering of stress.
Q: How to simulate the power supply filtering is often used LC circuit. However, I found that LC sometimes worse than the RC filter effect, is this is why, when the selected filter inductance, capacitance is what? . .
A.; LC and RC filtering effect of the comparison must be considered to be filtered out of the band and the choice of the inductance value is appropriate. Because the inductor gankang (reactance) size and inductance value and frequency. If the power of the low frequency noise, and the inductance value is large enough, maybe it's not RC filter effect. However, using RC filter costs is the resistance itself will consume energy, efficiency, and pay attention to the selected resistance can withstand the power.
In addition to considering the choice of inductance to filter out the noise frequency, but also consider the transient current response capacity. If the output of LC have the opportunity to require large instantaneous output current, the inductor value is too large current flows through the General Assembly hinder the speed of the inductor to increase the ripple noise (ripple noise). .
Capacitance values and can tolerate ripple noise specifications for the size of the value. Ripple noise values require smaller capacitance value. While the capacitor ESR/ESL will have an impact.
Also, if the LC is on the switch mode power supplies (switching regulation power) when the output should also pay attention to the LC arising from the pole zero (pole / zero) of negative feedback (negative feedback control) loop stability of . .
21. Number/ground connection.
Q: When a multiple number of PCB board / module function block, the conventional approach is to D / to separate, and connected at one point. In this way, a piece of PCB board to be chopped into several pieces, and how interconnected are Dacheng problem. However, another approach was adopted, namely, to ensure that D / A module separate layout, and the number of D / A signal trace each other do not pay * the case, the entire PCB 板 to do as segmentation, D / earth joined to the ground plane on the reason of doing so, experts teach. .
For the few/segregation because digital circuits in high and low voltage switch in power and generate noise, noise of size with the speed of the signal and the current size. If the plane is not divided by the number of regional circuit noise generated by a simulation of the circuit and district very close to the analog signal, even if you do not pay * signal, analog continues to be ground noise interference. That is not split in analog mode only in analog circuits from producing large area digital circuit area more distant. In addition, the digital-analog signal traces should not cross * the request because the faster speed digital signal its return current path (return current path) will try to take the line along the bottom near the digital signal to flow back to the source, if the number of model signal traces cross *, the return current noise generated by analog circuits will appear in the region. .
22. circuit board design and EMC!.
Q: The circuit board design if we consider EMC, will improve the lot of the cost. Will replied to EMC requirements as much as possible, it will not take too much cost pressure? Thank you. .
A: the PCB Board will increase the cost of EMC are usually due to the increase in the number of strata in order to enhance the shielding effect and increases the ferrite bead, choke, high-frequency harmonics suppression devices. In addition, typically required with other agencies or shield structure to make the entire system through EMC requirements. The following only PCB design skills provides several electromagnetic radiation produced by reducing the effect of the circuit.
1, as selected signal slope (slew rate) slower devices to reduce high frequency components generated by the signal. 2, note the location of high-frequency devices are placed, not too close to the external connector. .
3. takes note of the high-speed signal impedance matching, alignment and return current path (return current path) to reduce the high frequency of reflection and radiation.
4, the device's power pins in place adequate and appropriate in order to ease power supply decoupling capacitor on the noise level and the ground. Special attention to the frequency response of capacitance and temperature characteristics to meet the design requirements. .
5, external connector near can do proper segmentation and formation, and the connector to the nearest received chassis ground.
6, may be the proper use of ground guard / shunt traces in a number of special high-speed signals next. But pay attention to guard / shunt traces on the characteristic impedance of the alignment. .
7. power layer than formation choke 20H, h is the power of the distance between the strata.
23. GSM cell phone PCB design. .
Ask: ask the expert GSM phone PCB design requirements and tips.
A: The phone PCB design challenge is two things: First, board size, the second is a RF circuit. Because the available board space is limited, but several different characteristics of the circuit area, such as RF circuits, power circuits, analog voice circuits, digital circuits in general, they all have different design requirements. .
1, you must first RF and non-RF Circuit in fraternities do proper partition. Because the RF power supply, ground, and the more stringent the impedance design specifications.
2, because the plate size, may need to use blind buried vias (blind / buried via) to increase the alignment area. .
3. takes note of the voice analog circuit alignment, not by other RF Circuit, digital circuit, and so produce crosstalk phenomena. In addition to widen the left line spacing, you can also use ground guard trace suppression crosstalk.
4, the appropriate formation of the division to do, especially analog circuits to be especially careful not to be used by other circuits to noise. .
5. takes note of the various circuit regional signal return current path (return current path) to avoid the possibility of increased crosstalk.
24: pcb design what issues need attention? . .
For PCB design when it is necessary to pay attention to problems with the application of the product. Like digital circuits and circuit simulation that not all the same. The following are only approximate some principles to be aware of.
1, PCB stack of decisions; including the power supply layer, layer, alignment layer arrangement, the alignment direction of the alignment layer. These will affect the signal quality, even electromagnetic radiation. .
2, power and related alignment and through-hole (via) to wide, much.
3, different characteristics of the circuit of regional allocation. Good regional configuration of the ease of alignment, or even signal quality has a significant relationship. .
4, to meet the production factories manufacturing process to set DRC (Design Rule Check) and related design and test (if test point). Other electrical related to problems with the circuit characteristics have the absolute relationship between, for example, even if it is a digital circuit, whether or not to pay attention to the alignment of the characteristic impedance is going to be the circuit's speed and line length.
25. The high-speed PCB Design EMC, EMI problems. .
Q: the high-speed PCB design software when we are but on the set up of EMC, EMI rules to check, and what standards do designers to consider the rules for EMC, EMI? how do I set up a rule that I am using the CADENCE company software.
A: General EMI / EMC design requires taking into account the radiation (radiated) and conduction (conducted) two aspects. . The former part attributable to the higher frequency (> 30MHz) the latter part of the lower frequency (<30MHz). . So we can not only pay attention to the neglect of low-frequency high-frequency part. .
A good EMI/EMC design must first be taken into account when the layout of the device's location, PCB stacked arrangement, important online law, choice of devices, etc, if these do not advance a better arrangement, after the solution shibeigongban will increase costs. For example, the location of the clock generator try not to * close to the external connectors, high-speed signal to go as far as possible and pay attention to characteristics of the inner layer of continuous impedance matching with the reference to reduce the reflection, the device by pushing the signal slope (slew rate) as small as possible to reduce high frequency components, select the decoupling (decoupling / bypass) capacitor frequency response when attention to its compliance with requirements to reduce the noise power level. . Also, note the high frequency signal current return path to circuit area as small as possible (that is, loop impedance loop impedance as small as possible) to reduce radiation. .You can also use the segmentation of the way to control the range of high-frequency noise. Finally, the appropriate choice of PCB and shell place (chassis ground).
26. Impedance on the PCB design issues. .
Q: when high-speed PCB design to prevent reflection we should consider the impedance matching, but because of the PCB processing limits the impedance of the continuity and the simulation and to imitated, the schematic diagram of how to consider at design time? about IBIS model, I do not know where they are able to provide more accurate IBIS model library. Our download library, most of which are not very accurate, very indicative of the simulation.
A: In the design of high-speed PCB circuits, impedance matching is one of the design elements. The impedance method has the absolute alignment with the relationship, such as walking in the surface layer (microstrip) or the inner layer (stripline / double stripline), and the reference layer (power layer or stratum) of the distance, take line width, PCB materials, etc. will affect the alignment of the characteristic impedance value. That is to be determined after the wiring impedance.General simulation software line model or mathematical algorithms used by not taking into account some of the wiring resistance is not continuous, this time in the schematic diagram can only reserve some terminators (termination), such as in-line resistors, etc., to ease the alignment effect. Truly fundamental solution to the problem or wiring to avoid the occurrence of resistance is not continuous.
IBIS models directly affect the accuracy of simulation results. Basically, IBIS can be regarded as the actual chip I / O buffer electrical characteristics of the equivalent circuit of the information, usually obtained by the SPICE model transformation (can be used to measure, but more limited), while SPICE data and chip manufacturers have absolute relations, so as to provide a device of different chip makers, which SPICE data is different, and then converted the data within the IBIS model will follow another.In other words, if you use A manufacturer's device, only they have the ability to provide accurate information on their device model, because no other person will be better than their device is determined by what process. If vendors IBIS inaccurate, can only continue to require the manufacturer to improve is the fundamental solution.
27. Comparison of PCB design tools. .
Q: what is your personal point of view: for analog circuits (microwave, RF, low frequency), the digital circuit (microwave, RF, low frequency), analog and digital hybrid circuits (microwave, RF, low frequency), the current PCB design which EDA tools for a better price-performance (including simulations)? Please describe.
A: The limited understanding of my application, not in-depth comparison of cost performance EDA tools, select the scope of application software in accordance with the terms, I advocate the principle is good enough. .
Conventional circuit design, INNOVEDA's PADS are very good, and are used for simulation software, and such a design often occupies 70% of the applications. At the high-speed circuit design, analog and digital hybrid circuits, using Cadence solution should belong to the performance and price comparison of good software, of course, the performance of the Mentor or very good, particularly its design process management should be the most outstanding.
The above observations are purely personal views! . .
28. with regard to the d/a separate layout and smart layout.
Q: When a system is the foundation that RF small signal, another high-speed clock signal, usually we use D / A separation of layout, by physical isolation, filtering, etc. to reduce electromagnetic interference, but this is for small, high integration and reduction processing costs of small structures is of course negative, but results are still not satisfactory, because either analog or digital ground take place, the final will receive case to go up, making interference coupled through the ground to the front end, which is our very headache problem, would like to ask experts in this area measures. .
A: both small-signal, RF and high-speed clock signal is more complex, the cause of the interference needed careful analysis, and appropriate to try to resolve it. To follow the specific application, you can try the following methods. 0: there is a small-signal, RF, high-speed clock signal, the first thing is to separate the power supply, it is not advisable to use switching power supply, you can use linear power supply.
1: Select the RF small-signal, high-speed clock signal which a signal, shielded cable to connect the way, should be able to. .
2: number-the power of connection (requires power of isolation is better), analog sites received the case on the ground.
3: try to remove interference filter approach. .
